Modern high-speed digital communication systems employ data transmit and recovery circuits operating at or above ten gigabits per second. Due to the bandwidth limitations of conventional CMOS processes, it is difficult to produce an amplifier capable of driving a significant load with better than unity gain at frequencies above about five gigahertz (GHz). At frequencies approaching five GHz, amplifier gain is at the tail portion of the roll-off characteristic.
FIG. 1A (prior art) is a Bode plot depicting a roll-off characteristic for a typical CMOS amplifier. The roll-off (xe2x88x923 dB) frequency Fo is around several hundred MHz. More exotic processes, such as those employing silicon germanium or gallium arsenide, provide improved high-frequency response; unfortunately, this improvement comes at considerable expense.
FIG. 1B (prior art) depicts a communication system 100 that includes a transmitting integrated circuit (IC) 105 and a receiving IC 110. Transmitting IC 105 includes an output amplifier 115 driving an external pin 120 via a bond pad 125 and a bond wire 130. An electrostatic-discharge (ESD) circuit 135 connects to bond pad 125 and the output of amplifier 115 to protect IC 105 from damage due to ESD events. IC 110 includes an input amplifier 140 that receives the output of IC 105 via a printed-circuit-board (PCB) trace 145, an input pin 150, a bond wire 155, and a bond pad 160. IC 110 also includes an ESD circuit 165 connected to the signal line between pad 160 and the input to amplifier 140.
System 100 illustrates that amplifiers intended to drive signals off chip must contend with capacitive loading far greater than normally experienced on chip. Such signals encounter capacitive loading from e.g. bond pads 125 and 160, bond wires 130 and 155, ESD circuits 135 and 165, PCB trace 145, and the input of amplifier 140. These capacitances collectively shift the pole of output amplifier 115 toward zero, exacerbating the problem of communicating at high frequency.
Also problematic, increased load capacitance reduces amplifier bandwidth. The unity-gain bandwidth of amplifier 115 is defined by gm/Cld, where gm is the amplifier transconductance and Cld is the capacitive load on the amplifier. Load capacitance Cld is typically in the neighborhood of 1.2 pf, providing a bandwidth typically in the range of several hundred megahertz.
An article by Savoj and Razavi entitled xe2x80x9cA 10 Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detection,xe2x80x9d 2001 IEEE International Solid-State Circuits Conference, describes a CDR circuit that addresses the problem of providing high-frequency signals off chip using relatively inexpensive CMOS processes. That article is incorporated herein by reference.
FIG. 2 (prior art) depicts the output buffer (amplifier) 200 described in the Savoj and Razavi article. Buffer 200 includes an input stage 205 and an output stage 210. Output stage 210 experiences the capacitive loading described above in connection with FIG. 1B. The transistors associated with output stage 210 are relatively large, helping output stage 210 contend with the load. Due to their size, the transistors of output stage 210 present a significant capacitive load (e.g., 0.5 picofarads) to input stage 205. Input stage 205 employs inductive peaking to increase high-frequency, small-signal gain in the face of the input capacitance of output stage 210Still, there is always a demand for higher performance.
A buffer in accordance with the invention employs an input stage with an active, LC load. The active load includes integrated inductors that combine with the parasitic gate capacitances of a pair of transistors in a negative-transconductance (xe2x88x92Gm) booster configuration. The resulting active load emphasizes a desired frequency, improving the quality, or xe2x80x9cQ,xe2x80x9d of the input stage, and consequently of the entire buffer.
This summary does not define the scope of the invention, which is instead defined by the appended claims.